1. Technical Field
The disclosure relates to a data access circuit of a semiconductor memory device and, more particularly, to a data access circuit of a semiconductor memory device in which data is read and written via all multiple ports in a semiconductor memory device having a multi-port structure.
2. Discussion of the Related Art
Generally, a random access memory device is a type of digital memory device having memory cells for storing bit data and digital data therein. Any of the memory cells can be addressed and accessed independent of other memory cells.
A random access memory (RAM) includes a read only memory (ROM) and a read/write memory (RWM). Both ROM and RWM include various static load, synchronous, and asynchronous memory devices. Further, in the RAM, there are static memory architecture and dynamic memory architecture. The static memory architecture has some storage configurations with latches while the dynamic memory architecture has some storage configurations in which charges are dynamically stored in capacitors.
Dynamic RAMs (DRAMs) and synchronous dynamic RAMs (SDRAMs) are types of dynamic architectures being commercially and widely used in various types of digital devices. In particular, the SDRAMs are being extensively used because of its fast accessibility. Memory cells of a memory array in the SDRAM are normally divided into banks. Further, the SDRAMs include circuitry for allowing an operation of a ‘burst mode.’ In the burst mode, the memory cells are accessible at a much higher access speed than can be realized with memory cells of a conventional asynchronous DRAM.
The SDRAMs undergo a test in a manufacture process in order to confirm whether the memory cells operate properly. During the testing process, data of a known value is written to memory cells in the memory array bank, like other types of memory devices. Data is applied by various addressing sequences, typically to all memory cells in the memory array.
In the case of the SDRAMs, a time needed to write data to all memory cells in the banks of the memory array increases as the capacity of the SDRAM increases, like other memory devices. Such increasing amount of time reduces the throughput of the memory devices in the testing process.
The SDRAM is designed to comply with standards and communication protocols defined by the Joint Electronic Device Engineering Council (JEDEC). Present standards and communication protocols by the JEDEC include a defined signal protocol for a signal which causes the memory cells of the SDRAM to be addressed. For instance, an address select signal is defined. The address select signal, when applied to the SDRAM, enables the memory cells of the SDRAM to be addressed.
Upon testing the SDRAM, a series of address select signals are applied to the memory device, and the memory cells of the memory device are addressed in response to values of the address select signals. Data is written sequentially to the addressed memory cells.
Typically, a software algorithm is executed by a processor and the address select signals are generated onto address select lines. The memory cells are addressed in response to values of the address select signals, which are generated on all address select lines applied to the SDRAM except for a next bit to the most significant bit. Accordingly, upon testing the SDRAM, it is impossible to access all memory cells of the SDRAM only with the address select signals that are incremented by one bit, in which the address select signals are generated by a software algorithm used to generate the address select signals.
To solve this problem, a technique capable of simultaneously addressing columns for a plurality of memory banks, and at the same time, of simultaneously writing data to the memory cells in a SDRAM or a memory device having a plurality of memory banks, is disclosed in U.S. Pat. No. 5,671,392. In U.S. Pat. No. 5,671,392, the column of the memory banks can be addressed concurrently and the data can be read and/or written concurrently.
In addition, a multi-port access memory in which an address decoder and read/write data paths for read and write are shared, thus reducing the size of the memory, is disclosed in U.S. Pat. No. 6,122,218.
In such a semiconductor memory device having a multi-port structure, however, one port serves as a read/write port and all input/output lines share the same bits at all ports.
FIG. 1 is a diagram illustrating a write data line control circuit of a conventional semiconductor memory device having a multi-port structure.
The control circuit is composed of a write controller 10 enabled by a write control signal Write to receive a column cycle signal Colcyc and output an input/output driver enable signal; first to fourth ports 20, 22, 24, and 26 receive serial data, each converting the serial data to 512-bit parallel data, and then outputting the parallel data; a first write buffer unit 30 for buffering the 512-bit parallel data received from the first port 20 to output the buffered parallel data to data lines 40 in response to a first port select signal load_P0; a second write buffer unit 32 for buffering the 512-bit parallel data received from the second port 22 to output the buffered parallel data to the data lines 40 in response to a second port select signal load_P1; a third write buffer unit 34 for buffering the 512-bit parallel data received from the third port 24 to output the buffered parallel data to the data lines 40 in response to a third port select signal load_P2; a fourth write buffer unit 36 for buffering the 512-bit parallel data, received from the fourth port 26, to output the buffered parallel data to the data lines 40 in response to a fourth port select signal load_P3; an input/output driver 50 for receiving the 512-bit data, inputted from the data lines 40, to output the received data to input/output lines IO0 to IO511 in response to the input/output driver enable signal from the write controller 10.
FIG. 2 is a write timing diagram of a conventional semiconductor memory device.
The operation for controlling data lines upon writing data will be described with reference to FIGS. 1 and 2. In order to write the data to memory cells, when receiving an address Addre and a column latch signal Collat as shown in FIG. 2, a column decoder (not shown) generates a column select signal CSL and connects bit lines with the input/output lines IQ0 to IQ511. The write controller 10 is enabled by a write control signal Write as shown in FIG. 2 to receive a column cycle signal Colcyc, also shown FIG. 2, and output the input/output driver enable signal to the input/output driver 50. At this time, serial data to be written is applied to the first to fourth ports 20, 22, 24, and 26. The first to fourth ports 20, 22, 24, and 26 receive the serial data, convert the serial data to 512-bit parallel data PORT0 to PORT3 as shown in FIG. 2, and output the parallel data to the first to fourth write buffer units 30, 32, 34, and 36. At this time, first to fourth port select signals load_P0 to load_P3 are sequentially generated in one cycle unit of the column latch signal Collat as shown in FIG. 2. The first to fourth write buffer units 30, 32, 34, and 36 sequentially output 512-bit write data WD as shown FIG. 2 to the data lines 40 in response to the first to fourth port select signals load_P0 to load_P3. At this time, the 512-bit data inputted from one port is mapped with one column address. The 512-bit data, outputted to the data lines 40, is applied to the input/output driver 50. The input/output driver 50 outputs the 512-bit data, applied onto the data lines 40, to the input/output line I/O0 to I/O511 in response to the input/output driver enable signal from the write controller 10.
FIG. 3 is a diagram illustrating a read data line control circuit of a conventional semiconductor memory device having a multi-port.
The control circuit is composed of a read controller 100 enabled by an inverted write control signal Write to receive a column cycle signal Colcyc and output an input/output sense amplifier enable signal; an input/output sense amplifier 140 for receiving 512-bit read data inputted from input/output lines I/O0 to I/O511 to output the read data to the data lines 130 in response to the input/output sense amplifier enable signal from the read controller 100; a first read buffer unit 120 for buffering the 512-bit parallel data inputted from the data lines 130 to output the buffered parallel data to the first port 110 in response to the first port select signal load_P0; a second read buffer unit 122 for buffering the 512-bit parallel data inputted from the data lines 130 to output the buffered parallel data to a second port 112 in response to a second port select signal load_P1; a third read buffer unit 124 for buffering the 512-bit parallel data inputted from the data lines 130 to output the buffered parallel data to a third port 114 in response to a third port select signal load_P2; a fourth read buffer unit 126 for buffering the 512-bit parallel data inputted from the data lines 130 to output the buffered parallel data to a fourth port 116 in response to a fourth port select signal load_P3; and the first to fourth ports 110, 112, 114, and 116 for receiving the 512-bit parallel data from the first to fourth read buffer units 120, 122, 124, and 126, converting the received parallel data to serial data, and output the converted serial data.
FIG. 4 is a read timing diagram of a conventional semiconductor memory device.
The operation for controlling the data lines upon reading data will be described with reference to FIGS. 3 and 4. In order to read the data stored in the memory cell, when receiving an address Addr and a column latch signal Collat as shown in FIG. 4, a column decoder (not shown) generates a column select signal CSL and connects the bit line to the input/output lines I/O0 to I/O511. The read controller 100 is enabled by the write control signal Write inverted as shown in FIG. 4 to receive a column cycle signal Colcyc and output an input/output sense amplifier enable signal to the input/output sense amplifier 140. At this time, the 512-bit data, read from the memory cells, are applied to the I/O sense amplifier 140 via the input/output line I/O1 to I/O511. The input/output sense amplifier 140 is enabled by the input/output sense amplifier enable signal received from the read controller 100 to output the 512-bit parallel data onto the data lines 130. At this time, the first to fourth port select signals load_P0 to load_P3 are sequentially generated in one cycle unit of the column latch signal Collat, as shown in FIG. 4. The first to fourth read buffers 120, 122, 124, and 126 sequentially output 512-bit read data RD as shown in FIG. 4 to the first to fourth ports 110, 112, 114, and 116 in response to the first to fourth select signal load_P0 to load_P3. The first to fourth ports 110, 112, 114, and 116 sequentially output the read data Port0 to Port3 as shown in FIG. 4. Accordingly, the 512-bit data, outputted over an arbitrary column cycle upon the read operation, are adapted to be outputted via any one of the four ports, the first to fourth ports 110, 112, 114, and 116. For this reason, when it is assumed that data outputted during one column cycle is for example 512 bits, the 512-bit data are divided four times and then outputted via the first to fourth ports 110, 112, 114, and 116 since the number of the data outputted via one port is 512-bit data. Accordingly, if a column cycle operation time in the memory is ignored then a multi-port memory with four port units, namely the first to fourth ports 110, 112, 114, and 116 outputs data in four column read operations. A time to output the data at one of the first to fourth ports 110, 112, 114, and 116 is 2 μsec, when a system clock is for, example 100 MHz.
In the conventional memory device having a multi-port as described above, there is a problem that it takes about 2 μsec to output all 512 data bits because memory cell testing equipment is of a low frequency of about 25 MHz, and accordingly, a memory test time becomes several times to several tens of times longer as compared to a memory with 18 DQ, thus deteriorating the throughput.